SH7720 Datasheet, PDF (768/1524 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 21 Serial I/O with FIFO (SIOF)
21.3.12 Receive Data Assign Register (SIRDAR)
SIRDAR is a 16-bit readable/writable register that specifies the position of the receive data in a
frame (slot number).
Initial
Bit
Bit Name Value
15
RDLE
0
14 to 12 
All 0
11
RDLA3 0
10
RDLA2 0
9
RDLA1 0
8
RDLA0 0
7
RDRE 0
6 to 4 
All 0
3
RDRA3 0
2
RDRA2 0
1
RDRA1 0
0
RDRA0 0
R/W
R/W
R
R/W
R/W
R/W
R/W
R/W
R
R/W
R/W
R/W
R/W
Description
Receive Left-Channel Data Enable
0: Disables left-channel data reception
1: Enables left-channel data reception
Reserved
These bits are always read as 0. The write value should
always be 0.
Receive Left-Channel Data Assigns 3 to 0
Specify the position of left-channel data in a receive
frame as B'0000 (0) to B'1110 (14).
1111: Setting prohibited
• Receive data for the left channel is stored in the
SIRDL bit in SIRDR.
Receive Right-Channel Data Enable
0: Disables right-channel data reception
1: Enables right-channel data reception
Reserved
These bits are always read as 0. The write value should
always be 0.
Receive Right-Channel Data Assigns 3 to 0
Specify the position of right-channel data in a receive
frame as B'0000 (0) to B'1110 (14).
1111: Setting prohibited
• Receive data for the right channel is stored in the
SIRDR bit in SIRDR.
Rev. 3.00 Jan. 18, 2008 Page 706 of 1458
REJ09B0033-0300