SH7720 Datasheet, PDF (839/1524 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 24 USB Host Controller (USBH)
Initial
Bit
Bit Name Value R/W Description
4
UE
0
R/W Unrecoverable Error Enable
0: Ignored
1: Interrupt generation due to unrecoverable error enabled
3
RD
0
R/W Resume Detected Enable
0: Ignored
1: Interrupt generation due to Resume Detected enabled
2
SF
0
R/W Start of Frame Enable
0: Ignored
1: Interrupt generation due to Start of Frame enabled
1
WDH
0
R/W Write-back Done Head Enable
0: Ignored
1: Interrupt generation due to WritebackDoneHead
enabled
0
SO
0
R/W Scheduling Overrun Enable
0: Ignored
1: Interrupt generation due to Scheduling Overrun enabled
24.3.6 Hc Interrupt Disable Register (USBHID)
Each disable bit in USBHID corresponds to the related interrupt bit in USBHIS. USBHID is
related to USBHIE. Therefore, writing a 1 to a bit in this register clears the corresponding bit in
USBHIE, while writing a 0 to a bit leaves the corresponding bit in USBHIE. When read, the
current value of USBHIE is returned.
Initial
Bit
Bit Name Value R/W Description
31
MIE
0
R/W Master Interrupt Enable
0: Ignored
1: Interrupt generation due to the specified event disabled
30
OC
0
R/W Ownership Change Enable
0: Ignored
1: Interrupt generation due to OwnershipChange disabled
Rev. 3.00 Jan. 18, 2008 Page 777 of 1458
REJ09B0033-0300