SH7720 Datasheet, PDF (1469/1524 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Item
Page Revision (See Manual for Details)
Section 10 Direct Memory Access 409
Controller (DMAC)
10.2 Input/Output Pins
Table 10.1 Pin Configuration
Changed
Channel Name
Pin
Name
0
DMA transfer request DREQ0
DMA transfer request DACK0
reception
DMA transfer end TEND0
1
DMA transfer request DREQ1
DMA transfer request DACK1
reception
DMA transfer end TEND1
I/O
Input
Output
Output
Input
Output
Output
Section 10 Direct Memory Access 428
Controller (DMAC)
10.4.2 DMA Transfer Requests
(3)
Table 10.18 Example of BSC
447
Ordinary Memory Access (No
Wait, Idle Cycle 1, Longword
Access to 16-Bit Device)
Added
….Transfer request signals comprise the transmit data
empty transfer request and receive data full transfer
request from the ADC set by CHCR0 to CHCR5 and
the SCIF0, SCIF1, MMC, USBF, SIM, SIOF0, SIOF1,
and SDHI set by DMARS0/1/2,…. These conditions
also apply to the SIOF1, MMC, USBF, SIM, SIOF0,
SIOF1, and SDHI…..
Amended
CKIO
Address
T1 T2 Taw T1 T2
CSn
RD
Data
WEn
DACKn
(Active-low)
WAIT
10.5 Usage Notes
448
10.5.2 Notes on the Cases When
DACK is Divided
Note: The DACK is asserted for the last transfer unit
of the DMA transfer. When the transfer unit is
divided into several bus cycles and the CSn is
negated between bus cycles, the DACK is also
divided.
Section 10.5.2 added
Rev. 3.00 Jan. 18, 2008 Page 1407 of 1458
REJ09B0033-0300