SH7720 Datasheet, PDF (339/1524 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 8 Interrupt Controller (INTC)
Program
execution state
Interrupt
No
generated?
Yes
No
SR.BL=0,
sleep mode,
or standby mode?
Yes
Yes
Set interrupt source in
INTEVT and INTEVT2
Save SR to SSR;
save PC to SPC
Set BL, MD, and RB
bits in SR to 1
Branch to exception
handler
NMI?
Yes
No
Level 15
No
interrupt?
Yes
Level 14
No
interrupt?
I3 to I0 levels are
14 or lower?
Yes
Level 1
No
interrupt?
No
I3 to I0 levels are
Yes
Yes
13 or lower?
No
I3 to I0 levels are 0?
Yes
No
I3 to I0: Interrupt mask bits in status register (SR)
Figure 8.3 Interrupt Operation Flowchart
Rev. 3.00 Jan. 18, 2008 Page 277 of 1458
REJ09B0033-0300