SH7720 Datasheet, PDF (89/1524 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Classification Symbol
I/O
Interrupts
PINT15 to
I
PINT0
REFOUT
O
IRQOUT
O
Address bus
A25 to A0
O
Data bus
Bus control
D31 to D0
I/O
CS4 to CS2, O
CS0
CS6A, CS6B,
CS5A, CS5B,
CE2A, CE2B,
CE1A, CE1B
RD
O
RD/WR
O
BS
O
BACK
O
BREQ
I
WE
O
WE3 (BE3)
O
WE2 (BE2)
O
WE1 (BE1)
O
WE0 (BE0)
O
CKE
O
Section 1 Overview
Name
Function
Port interrupt Port interrupt request pins
requests 15 to 0
Bus request Bus request signal for refreshing
Bus request Bus request signal for interrupt
Address bus Outputs addresses.
Data bus
32-bit bidirectional data bus
Chip select
Chip-select signal for external
memory or devices.
Read strobe
Indicates reading of data from
external devices.
Read/write
signal
Read/write signal
Bus start
Bus-cycle start signal pin
Bus request
acknowledge
Indicates that the bus mastership
has been released to an external
device.
Bus request
Low when an external device
requests the release of the bus
mastership.
Write enable Write enable pin for PCMCIA
Highest-byte
write
Indicates that bits 31 to 24 of the
data in the external memory or
device are being written.
Second-highest- Indicates that bits 23 to 16 of the
byte write
data in the external memory or
device are being written.
Second-lowest- Indicates that bits 15 to 8 of the
byte write
data in the external memory or
device are being written.
Lowest-byte
write
Indicates that bits 7 to 0 of the data
in the external memory or device
are being written.
Clock enable Clock enable (SDRAM)
Rev. 3.00 Jan. 18, 2008 Page 27 of 1458
REJ09B0033-0300