SH7720 Datasheet, PDF (380/1524 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 9 Bus State Controller (BSC)
Initial
Bit
Bit Name Value R/W Description
2

0
R Reserved
This bit is always read as 0. The write value should always
be 0.
1
TRC1
0
R/W Number of Cycles from REF Command/Self-Refresh
0
TRC0
0
R/W ^{Release to ACTV Command}
Specify the number of minimum cycles from issuing the
REF command or releasing self-refresh to issuing the
ACTV command. The setting for areas 2 and 3 is
common.
00: 3 cycles
01: 4 cycles
10: 6 cycles
11: 9 cycles
Note: * If both areas 2 and 3 are specified as SDRAM, TRP1/0, TRCD0/1, TRWL1/0, and
TRC1/0 bit settings are common.
If only one area is connected to the SDRAM, specify area 3. In this case, specify area 2
as normal space or byte-selection SRAM.
Rev. 3.00 Jan. 18, 2008 Page 318 of 1458
REJ09B0033-0300