SH7720 Datasheet, PDF (1109/1524 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 31 MultiMediaCard Interface (MMCIF)
31.3.13 Interrupt Control Registers 0 and 1 (INTCR0 and INTCR1)
INTCR enable or disable each flag set of INTSTR0 and INTSTR1 and interrupts.
• INTCR0
Initial
Bit
Bit Name Value R/W Description
7
FEIE
0
R/W FIFO Empty Flag Enable
0: Disables FIFO empty flag setting
1: Enables FIFO empty flag setting
6
FFIE
0
R/W FIFO Full Flag Enable
0: Disables FIFO full flag setting
1: Enables FIFO full flag setting
5
DRPIE 0
R/W Data Response End Flag Enable
0: Disables data response end flag setting
1: Enables data response end flag setting
4
DTIE
0
R/W Data Transfer End Flag Enable
0: Disables data transfer end flag setting
1: Enables data transfer end flag setting
3
CRPIE 0
R/W Command Response End Flag Enable
0: Disables command response end flag setting
1: Enables command response end flag setting
2
CMDIE 0
R/W Command Output End Flag Enable
0: Disables command output end flag setting
1: Enables command output end flag setting
1
DBSYIE 0
R/W Data Busy End Flag Enable
0: Disables data busy end flag setting
1: Enables data busy end flag setting
0
BTIE
0
R/W Multiblock Transfer End Flag Enable
0: Disables multiblock transfer end flag setting
1: Enables multiblock transfer end flag setting
Rev. 3.00 Jan. 18, 2008 Page 1047 of 1458
REJ09B0033-0300