SH7720 Datasheet, PDF (270/1524 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 5 Cache
(2) Write Miss
In write-back mode, an external write cycle starts when a write miss occurs, and the entry is
updated. The way to be replaced is shown in table 5.4. When the U bit of the entry which is to be
replaced by entry updating is 1, the cache-update cycle starts after the entry has been transferred to
the write-back buffer. Data is written to the cache and the U bit and the V bit are set to 1. The
LRU is updated to indicate that the replaced way is the most recently updated way. After the cache
has completed its update cycle, the write-back buffer writes the entry back to the memory.
Transfer is in 16-byte units. In write-through mode, no write to cache occurs in a write miss; the
write is only to the external memory.
5.3.5 Write-Back Buffer
When the U bit of the entry to be replaced in write-back mode is 1, the entry must be written back
to the external memory. To increase performance, the entry to be replaced is first transferred to the
write-back buffer and fetching of new entries to the cache takes priority over writing back to the
external memory. After the fetching of new entries to the cache completes, the write-back buffer
writes the entry back to the external memory. During the write-back cycles, the cache can be
accessed. The write-back buffer can hold one line of cache data (16 bytes) and its physical
address. Figure 5.3 shows the configuration of the write-back buffer.
PA (31 to 4) Longword 0 Longword 1 Longword 2 Longword 3
PA (31 to 4):
Physical address written to external memory
Longword 0 to 3: One line of cache data to be written to external
memory
Figure 5.3 Write-Back Buffer Configuration
5.3.6 Coherency of Cache and External Memory
Use software to ensure coherency between the cache and the external memory. When memory
shared by this LSI and another device is placed in an address space to which caching applies, use
the memory-mapped cache to make the data invalid and written back, as required. Memory that is
shared by this LSI’s CPU and DMAC should also be handled in this way.
Rev. 3.00 Jan. 18, 2008 Page 208 of 1458
REJ09B0033-0300