SH7720 Datasheet, PDF (540/1524 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 13 Power-Down Modes
Table 13.1 shows the transition conditions for entering the modes from the program execution
state, as well as the CPU and peripheral module states in each mode and the procedures for
canceling each mode.
Table 13.1 States of Power-Down Modes
State
Mode
Transition
Conditions
CPG
CPU
CPU
Reg-
ister
On-Chip
Memory
On-Chip
Periphera External
l Modules Memory
Canceling
Procedure
Sleep
mode
Execute SLEEP Runs
instruction with
STBY bit in STBCR
cleared to 0
Halts
Held
Halts
Run
(contents
remained)
Auto-
• Interrupt
refreshing _{• Reset}
Software
Standby
mode
Execute SLEEP Halts
instruction with
STBY bit in STBCR
set to 1
Halts
Held
Halts
(contents
remained)
Halt*
Self-
• Interrupt
refreshing _{(NMI, IRQ}
(edge
detection),
RTC, TMU,
PINT
• Reset
Module
standby
function
Set MSTP bit in
STBCR to 1
Runs Runs/ Held
halts
Specified Specified
module halts module
(contents halts
remained)
Auto-
• Clear
refreshing _{MSTP bit to}
0
• Power-on
reset
Hardware Set CA pin to low
standby
mode
Halts Halts Held
Held
Halt*
Self-
• Power-on
refreshing _reset
Note: * The RTC operates when the START bit in RCR2 is set to 1. For details, see section 17,
Realtime Clock (RTC).
13.1.2 Reset
Resetting occurs when power is supplied, and when execution is started again from an initialized
state. There are two types of reset: A power-on reset and a manual reset. In a power-on reset, all
processing in execution is suspended, all unprocessed events are canceled, and reset processing
starts immediately. On the other hand, processing to retain the contents of external memory is
continued in a manual reset. The conditions for generating power-on and manual resets are as
follows.
Rev. 3.00 Jan. 18, 2008 Page 478 of 1458
REJ09B0033-0300