SH7720 Datasheet, PDF (1473/1524 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Item
Page Revision (See Manual for Details)
13.8 Hardware Standby Mode 496 Deleted
13.8.1 Transition to Hardware
Standby Mode
After entering software standby mode by the SLEEP
instruction, this LSI enters hardware standby mode by
driving the CA pin low.
Section 13 Power-Down Modes 498 Amended
Figure 13.12 Timing When Power
of Pins other than VCC_RTC and
VCCQ_RTC is Off
CA
RESETP
RTC protection
STATUS Normal*3 Standby*²
Undefined
Reset*1 Normal*3
Power supply
other than Vcc_RTC
and VccQ_RTC
0 to 10 Bcyc*4 0 to 30 Bcyc
Specification: Checking the standby state of the STATUS pin
Section 15 16-Bit Timer Pulse
Unit (TPU)
15.2 Input/Output Pins
Table 15.2 TPU Pin
Configurations
514
Notes: *1 Reset: HH (STATUS1 = High, STATUS0 = High)
*2 Standby: LH (STATUS1 = Low, STATUS0 = High)
*3 Normal operation: LL (STATUS1 = Low, STATUS0 = Low)
*4 Bcyc: Bus clock cycle
Changed
Channel Name
Pin Name I/O
0
TPU compare
TPU_TO0 Output
match output 0
1
TPU compare
TPU_TO1 Output
match output 1
2
TPU compare
TPU_TO2 Output
match output 2A
TPU clock input 2A TPU_TI2A Input
TPU clock input 2B TPU_TI2B Input
3
TPU compare
TPU_TO3 Output
match output 3A
TPU clock input 3A TPU_TI3A Input
TPU clock input 3B TPU_TI3B Input
Section 15 16-Bit Timer Pulse
Unit (TPU)
15.4.4 PWM Modes
536 Amended
Conditions of duty 0% and 100% are shown below.
• Duty
0%: The set value of the duty register
(TGRA) is TGRB + 1 for the period
register(TGRB).
• Duty 100%: The set value of the duty register
(TGRA) is 0.
Rev. 3.00 Jan. 18, 2008 Page 1411 of 1458
REJ09B0033-0300