SH7720 Datasheet, PDF (544/1524 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 13 Power-Down Modes
Initial
Bit
Bit Name Value R/W Description
5
MSTP8 0
R/W Module Stop Bit 8
When the MSTP8 bit is set to 1, the supply of the clock to
the DMAC is halted.
0: DMAC operates
1: Clock supply to DMAC halted
4
MSTP7 0
R/W Module Stop Bit 7
When the MSTP7 bit is set to 1, the supply of the clock to
the DSP is halted.
0: DSP operates
1: Clock supply to DSP halted
3
MSTP6 0
R/W Module Stop Bit 6
When the MSTP6 bit is set to 1, the supply of the clock to
the TLB is halted.
0: TLB operates
1: Clock supply to TLB halted
2
MSTP5 0
R/W Module Stop Bit 5
When the MSTP5 bit is set to 1, the supply of the clock to
the cache memory is halted.
0: Cache memory operates
1: Clock supply to cache memory halted
1

0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
0
MSTP3 0
R/W Module Stop Bit 3
When the MSTP3 bit is set to 1, the supply of the clock to
the X/Y memory is halted.
0: X/Y memory operates
1: Clock supply to X/Y memory halted
Rev. 3.00 Jan. 18, 2008 Page 482 of 1458
REJ09B0033-0300