SH7720 Datasheet, PDF (1094/1524 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 31 MultiMediaCard Interface (MMCIF)
Initial
Bit
Bit Name Value R/W Description
7
—
0
R Reserved
This bit is always read as 0. The write value should always
be 0.
6
TY6
0
R/W Specifies the pre-defined multiblock transfer. Bits TY1 and
TY0 should be set to 01 or 10.
When the command which specifies this bit is used, the
transfer block size and the number of transfer blocks should
be specified in TBCR and TBNCR, respectively.
5
TY5
0
R/W Specifies the multiblock transfer while the secure MMC is
used. Bits TY1 and TY0 should be set to 01 or 10.
When the command which specifies this bit is used, the
transfer block size and the number of transfer blocks should
be specified in TBCR and TBNCR, respectively.
4
TY4
0
R/W This bit is set to 1 when the CMD12 command is issued. Bits
TY1 and TY0 should be set to 00.
3
TY3
0
R/W Specifies the stream transfer. Bits TY1 and TY0 should be
set to 01 or 10. The stream transfer can be used only in
MMC mode.
The command sequence of the stream transfer specified by
this bit ends when it is stopped by the CMD12 command.
2
TY2
0
R/W Specifies the open-ended multiblock transfer. Bits TY1 and
TY0 should be set to 01 or 10.
The command sequence of the stream transfer specified by
this bit ends when it is stopped by the CMD12 command.
1
TY1
0
R/W Specify the existence and direction of transfer data.
0
TY0
0
R/W 00: A command without data transfer
01: A command with read data reception
10: A command with write data transmission
11: Setting prohibited
Table 31.2 summarizes the correspondence between the commands described in the
MultiMediaCard System Specification Version 3.1 and the settings of CMDTYR and RSPTYR.
Rev. 3.00 Jan. 18, 2008 Page 1032 of 1458
REJ09B0033-0300