SH7720 Datasheet, PDF (672/1524 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 18 Serial Communication Interface with FIFO (SCIF)
Bit Bit Name Initial Value R/W
7
RTRG1
0
R/W
6
RTRG0
0
R/W
5
TTRG1
0
R/W
4
TTRG0
0
R/W
3
MCE
0
R/W
Description
Trigger of the Number of Receive FIFO Data 1, 0
Set the number of receive data which sets the
receive data full (RDF) flag in the serial status
register (SCSSR). These bits set the RDF flag when
the number of receive data stored in the receive
FIFO data register (SCFRDR) is increased more
than the number of setting triggers listed below.
00: 1
01: 16
10: 32
11: 48
Trigger of the Number of Transmit FIFO Data 1, 0
Set the number of remaining transmit data which
sets the transmit FIFO data register empty (TDFE)
flag in the serial status register (SCSSR). These bits
set the TDFE flag when the number of transmit data
in the transmit FIFO data register (SCFTDR) is
decreased less than the number of setting triggers
listed below.
00: 32 (32)
01: 16 (49)
10: 2 (62)
11: 0 (64)
Note: * Values in brackets mean the number of
empty bytes in SCFTDR when the TDFE
is set.
Modem Control Enable
Enables the modem control signals CTS and RTS.
0: Disables the modem signal*
1: Enables the modem signal
Note: * The CTS is fixed to active 0 regardless
of the input value, and the RTS is also
fixed to 0.
Rev. 3.00 Jan. 18, 2008 Page 610 of 1458
REJ09B0033-0300