SH7720 Datasheet, PDF (943/1524 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 26 LCD Controller (LCDC)
26.3.11 LCDC Horizontal Sync Signal Register (LDHSYNR)
LDHSYNR specifies the timing of the generation of the horizontal (scan direction) sync signals
for the LCD module.
Bit Bit Name Initial Value R/W Description
15
HSYNW3 0
R/W Horizontal Sync Signal Width
14
HSYNW2 0
13
HSYNW1 0
12
HSYNW0 0
R/W Set the width of the horizontal sync signals (CL1 and
R/W ^{Hsync) (unit: character = 8 dots).}
R/W ^{Specify to the value of (the number of horizontal sync}
signal width) -1.
Example: For a horizontal sync signal width of 8 dots.
HSYNW = (8 dots/8 dots/character) -1 = 0 =
H'0
11 to 8 
All 0
R
Reserved
These bits are always read as 0. The write value
should always be 0.
7
HSYNP7 0
R/W Horizontal Sync Signal Output Position
6
HSYNP6 1
5
HSYNP5 0
4
HSYNP4 1
3
HSYNP3 0
2
HSYNP2 0
1
HSYNP1 0
0
HSYNP0 0
R/W Set the output position of the horizontal sync signals
R/W ^{(unit: character = 8 dots).}
R/W ^{Specify to the value of (the number of horizontal sync}
signal output position) -1.
R/W
Example: For a LCD module with a width of 640 pixels.
R/W
HSYNP = [(640/8) +1] -1 = 80 = H'50
R/W
In this case, the horizontal sync signal is
R/W
active from the 648th through the 655th dot.
Note: The following conditions must be satisfied:
HTCN ≥ HSYNP+HSYNW+1
HSYNP ≥ HDCN+1
Rev. 3.00 Jan. 18, 2008 Page 881 of 1458
REJ09B0033-0300