SH7720 Datasheet, PDF (468/1524 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 9 Bus State Controller (BSC)
(3) On-Chip Peripheral Module Access
To access an on-chip module register, two or more peripheral module clock (Pφ) cycles are
required. Care must be taken in system design.
(4) External Bus Priority Order
Access via an external bus is performed in the priority order below:
BREQ > Refresh > LCDC > USBH > DMAC > CPU
Note that next transfer is not performed until current transfer (e.g. burst transfer) has completed.
Rev. 3.00 Jan. 18, 2008 Page 406 of 1458
REJ09B0033-0300