SH7720 Datasheet, PDF (770/1524 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 21 Serial I/O with FIFO (SIOF)
Initial
Bit Bit Name Value R/W Description
3
CD1A3 0
R/W Control Channel 1 Data Assigns 3 to 0
2
CD1A2 0
1
CD1A1 0
0
CD1A0 0
R/W Specify the position of control channel 1 data in a receive
R/W ^{or transmit frame as B'0000 (0) to B'1110 (14).}
R/W ^{1111: Setting prohibited}
• Transmit data for the control channel 1 data is
specified in the SITD1 bit in SITCR.
• Receive data for the control channel 1 data is stored
in the SIRD1 bit in SIRCR.
Rev. 3.00 Jan. 18, 2008 Page 708 of 1458
REJ09B0033-0300