SH7720 Datasheet, PDF (843/1524 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 24 USB Host Controller (USBH)
24.3.12 Hc Bulk Current ED Register (USBHBCED)
USBHBCED includes a physical address of current ED in the Bulk List. When the bulk list is
supplied by the round robin method, endpoints are ordered to the list according to these insertions.
Initial
Bit
Bit Name Value R/W Description
31 to 4 BCED27 to All 0
BCED0
R/W BCED
Physical address of current ED in the Bulk List
3 to 0 
All 0 R Reserved
These bits are always read as 0. The write value should
always be 0.
24.3.13 Hc Done Head ED Register (USBHDHED)
USBHDHED includes a physical address of finally completed TD added to Done queue. The host
controller driver needs not read this register so that the content is written to HCCA periodically in
normal operation.
Bit
31 to 4
Bit Name
DH27 to
DH0
3 to 0 
Initial
Value R/W Description
All 0 R DH
Physical address of finally completed TD added to Done
queue
All 0 R Reserved
These bits are always read as 0. The write value should
always be 0.
24.3.14 Hc Fm Interval Register (USBHFI)
USBHFI includes a 14-bit value indicating the bit time interval of the frame (i.e., between two
serial SOFs) and a 15-bit value indicating the maximum packet size at a full speed that is
transmitted and received by the host controller without causing scheduling overrun. The host
controller driver adjusts the frame interval minutely by writing a new value over the current value
in each SOF.
Rev. 3.00 Jan. 18, 2008 Page 781 of 1458
REJ09B0033-0300