SH7720 Datasheet, PDF (618/1524 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 16 Compare Match Timer (CMT)
16.3.3 Timing for Counting by CMCNT
In this module, the clock for the counter can be selected from among the following:
• For channels 0 to 4:
 Peripheral clock (Pφ): 1/8, 1/32, or 1/128
The clock for the counter is selected by bits CKS2 to CKS0 in CMCSR. CMCNT is incremented
at the rising edge of the selected clock.
16.3.4 DMA Transfer Requests and Internal Interrupt Requests to CPU
The setting of bits CMR1 and CMR0 in CMCSR selects the sending of a request for a DMA
transfer or for an internal interrupt to the CPU at a compare match.
A DMA transfer request has different specifications according to the CMT channel as described
below.
1. For channels 0 and 1, a single DMA transfer request is output at a compare match.
2. For channels 2 to 4, a DMA transfer request continues until the amount of data transferred has
reached the value set in the DMAC, and the output of the request then automatically stops.
To clear the interrupt request, the CMF bit should be set to 0. Set the CMF bit to 0 in the handling
routine for the CMT interrupt.
Rev. 3.00 Jan. 18, 2008 Page 556 of 1458
REJ09B0033-0300