SH7720 Datasheet, PDF (1509/1524 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Item
Page Revision (See Manual for Details)
38.4.16 LCDC Module Signal
Timing
1368
Table 38.20 LCDC Module Signal
Timing
Conditions added
Conditions: V Q = 2.7 to 3.6 V, V Q1 = 2.7 to 3.6 V or
CC
CC
1.65 to 1.95 V, V = 1.4 to 1.6 V, AV = 3.0 to 3.6 V,
CC
CC
Ta = -20 to 75°C
38.4.17 SIM Module Signal
Timing
Table 38.21 SIM Module Signal
Timing
1369 Changed
Conditions: V Q = 2.7 to 3.6 V, V Q1 = 2.7 to 3.6 V or
CC
CC
1.65 to 1.95 V, V = 1.4 to 1.6 V, AV = 3.0 to 3.6 V,
CC
CC
Ta = -20 to 75°C
Item
Symbol Min.
Max.
SIM_CLK clock
cycle
t
SMCYC
2 x tpcyc 16 x tpcyc
38.4.18 MMCIF Module Signal
Timing
Table 38.22 MMCIF Module
Signal Timing
1370 Changed
Conditions: V Q = 2.7 to 3.6 V, V Q1 = 2.7 to 3.6 V or
CC
CC
1.65 to 1.95 V, V = 1.4 to 1.6 V, AV = 3.0 to 3.6 V,
CC
CC
Ta = -20 to 75°C
38.4.19 H-UDI Related Pin Timing 1372
Table 38.23 H-UDI Related Pin
Timing
Conditions: VccQ = VccQ_RTC = 2.7 to 3.6 V, VccQ1 =
2.7 to 3.6 V or 1.65 to 1.95 V, Vcc = Vcc_PLL1 = Vcc
_PLL2 = Vcc_RTC = 1.4 to 1.6 V, AVcc = AVcc_USB =
3.0 to 3.6 V, Ta = -20 to 75°C
Table 38.24 and 38.25
1374 Condition changed
[Before change] AVcc = 3.3 ± 0.3V → [After change]
AVcc = 3.0 to 3.6 V
38.7 AC Characteristic Test
Conditions
1375 Changed
• Input pulse level: VccQ to VssQ, VccQ1 to VssQ1
Rev. 3.00 Jan. 18, 2008 Page 1447 of 1458
REJ09B0033-0300