SH7720 Datasheet, PDF (214/1524 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 3 DSP Operating Unit
3.6.3 Single-Data Transfer Instructions
Table 3.37 Single Data Transfer Instructions
Instruction
Instruction Code Operation
Execution
States
DC Category
MOVS.W @-As,Ds
111101AADDDD0000 As-2 → As, (As) → MSW of 1
–
Ds, 0 → LSW of Ds
MOVS.W @As,Ds
111101AADDDD0100 (As) → MSW of Ds, 0
1
–
→ LSW of Ds
MOVS.W @As+,Ds 111101AADDDD1000 (As) → MSW of Ds, 0
1
–
→ LSW of Ds, As + 2 → As
MOVS.W @As+Ix,Ds 111101AADDDD1100 (Asc) → MSW of Ds, 0
1
–
→ LSW of Ds, As + Ix → As
MOVS.W Ds,@-As
111101AADDDD0001 As-2 → As, MSW of Ds
1
→ (As)
–*
MOVS.W Ds,@As
111101AADDDD0101 MSW of Ds → (As)
1
–*
MOVS.W Ds,@As+
111101AADDDD1001 MSW of Ds → (As), As + 2 1
→ As
–*
MOVS.W Ds,@As+Ix 111101AADDDD1101 MSW of Ds → (As), As + Ix 1
→ As
–*
MOVS.L @-As,Ds
111101AADDDD0010 As-4 → As, (As) → Ds
1
–
MOVS.L @As,Ds
111101AADDDD0110 (As) → Ds
1
–
MOVS.L @As+,Ds
111101AADDDD1010 (As) → Ds, As + 4 → As
1
–
MOVS.L @As+Ix,Ds 111101AADDDD1110 (As) → Ds, As + Ix → As 1
–
MOVS.L Ds,@-As
111101AADDDD0011 As-4 → As, Ds → (As)
1
–
MOVS.L Ds,@As
111101AADDDD0111 Ds → (As)
1
–
MOVS.L Ds,@As+
111101AADDDD1011 Ds → (As), As + 4 → As
1
–
MOVS.L Ds,@As+Ix 111101AADDDD1111 Ds → (As), As + Ix → As 1
–
Note: * If guard bit registers A0G and A1G are specified in source operand Ds, the data is
output to the LDB[7:0] bus and the sign bit is copied into the upper bits, [31:8].
Rev. 3.00 Jan. 18, 2008 Page 152 of 1458
REJ09B0033-0300