SH7720 Datasheet, PDF (886/1524 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 25 USB Function Controller (USBF)
25.3.25 EP1 Receive Data Size Register (EPSZ1)
EPSZ1 is a receive data size resister for endpoint 1. EPSZ1 indicates the number of bytes received
from the host. FIFO of endpoint 1 has a dual-buffer configuration. The size of the received data
indicated by this register is the size of the currently selected side (can be read by CPU).
Bit Bit Name
7 to 0 
Initial Value R/W Description
All 0
R Number of received bytes for endpoint 1
25.3.26 EP4 Receive Data Size Register (EPSZ4)
EPSZ4 is a receive data size resister for endpoint 4. EPSZ4 indicates the number of bytes received
from the host. FIFO of endpoint 4 has a dual-buffer configuration. The size of the received data
indicated by this register is the size of the currently selected side (can be read by CPU).
Bit Bit Name
7 to 0 
Initial Value R/W Description
All 0
R Number of received bytes for endpoint 4
25.3.27 Trigger Register (TRG)
TRG generates one-shot triggers FIFO for each endpoint of EP0s, EP0i, EP0o, EP1, EP2, and
EP3. The packet enable trigger for the IN FIFO register and read complete trigger for the OUT
FIFO register are triggers to be given.
Bit Bit Name
7

6
EP3 PKTE
5
EP1 RDFN
4
EP2 PKTE
3

2
EP0s RDFN
1
EP0o RDFN
0
EP0i PKTE
Initial Value R/W Description
0
W Reserved
The write value should always be 0.
0
W EP3 Packet Enable
0
W EP1 Read Complete
0
W EP2 Packet Enable
0
W Reserved
The write value should always be 0.
0
W EP0s Read Complete
0
W EP0o Read Complete
0
W EP0i Packet Enable
Rev. 3.00 Jan. 18, 2008 Page 824 of 1458
REJ09B0033-0300