SH7720 Datasheet, PDF (483/1524 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 10 Direct Memory Access Controller (DMAC)
• DMARS1
Initial
Bit
Bit Name Value R/W Description
15
C3MID5 0
14
C3MID4 0
13
C3MID3 0
R/W Transfer request module ID5 to ID0 for DMA channel 3
R/W ^(MID)
R/W ^{See table 10.2.}
12
C3MID2 0
R/W
11
C3MID1 0
R/W
10
C3MID0 0
R/W
9
C3RID1 0
8
C3RID0 0
R/W Transfer request register ID1 and ID0 for DMA channel 3
R/W ^(RID)
See table 10.2.
7
C2MID5 0
6
C2MID4 0
5
C2MID3 0
R/W Transfer request module ID5 to ID0 for DMA channel 2
R/W ^(MID)
R/W ^{See table 10.2.}
4
C2MID2 0
R/W
3
C2MID1 0
R/W
2
C2MID0 0
R/W
1
C2RID1 0
0
C2RID0 0
R/W Transfer request register ID1 and ID0 for DMA channel 2
R/W ^(RID)
See table 10.2.
Rev. 3.00 Jan. 18, 2008 Page 421 of 1458
REJ09B0033-0300