SH7720 Datasheet, PDF (733/1524 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 20 I²C Bus Interface (IIC)
Start
Initialize
Read BBSY in ICCR2
No
BBSY=0 ?
Yes
Set MST and TRS
in ICCR1 to 1.
Write 1 to BBSY
and 0 to SCP.
Write transmit data
in ICDRT
Read TEND in ICSR
No
TEND=1 ?
Yes
Read ACKBR in ICIER
ACKBR=0 ?
No
Yes
Transmit
No
mode?
Yes
Write transmit data in ICDRT
Read TDRE in ICSR
No
TDRE=1 ?
Yes
No
Last byte?
Yes
Write transmit data in ICDRT
Read TEND in ICSR
No
TEND=1 ?
Yes
Clear TEND in ICSR
Clear STOP in ICSR
Write 0 to BBSY
and SCP
Read STOP in ICSR
No
STOP=1 ?
Yes
Set MST and
TRS to 0 in ICCR1
Clear TDRE in ICSR
End
[1] Test the status of the SCL and SDA lines.
[2] Set master transmit mode.
[1]
[3] Issue the start candition.
[2] ^{[4] Set the first byte (slave address + R/W) of transmit data.}
[3] ^{[5] Wait for 1 byte to be transmitted.}
[4] ^{[6] Test the acknowledge transferred from the specified slave device.}
[7] Set the second and subsequent bytes (except for the final byte) of transmit data.
[5] [8] Wait for ICDRT empty.
[9] Set the last byte of transmit data.
[6] [10] Wait for last byte to be transmitted.
[11] Clear the TEND flag.
Mater receive mode
[7] ^{[12] Clear the STOP flag.}
[13] Issue the stop condition.
[8]
[14] Wait for the creation of stop condition.
[15] Set slave receive mode. Clear TDRE.
[9]
[10]
[11]
[12]
[13]
[14]
[15]
Figure 20.14 Sample Flowchart for Master Transmit Mode
Rev. 3.00 Jan. 18, 2008 Page 671 of 1458
REJ09B0033-0300