SH7720 Datasheet, PDF (280/1524 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 7 Exception Handling
Figure 7.1 shows the bit configuration of each register.
31
0
10 9
21 0
TRA 0
TRA
31
0
12 11
EXPEVT
0
EXPEVT
31
0
12 11
INTEVT
0
INTEVT
31
0
12 11
INTEVT2
0
INTEVT2
31
TEA
0
TEA
Figure 7.1 Register Bit Configuration
7.1.1 TRAPA Exception Register (TRA)
TRA is assigned to address H'FFFFFFD0 and consists of the 8-bit immediate data (imm) of the
TRAPA instruction. TRA is automatically specified by the hardware when the TRAPA instruction
is executed. Only bits 9 to 2 of the TRA can be re-written using the software.
Initial
Bit
Bit Name Value R/W Description
31 to 10 

R
Reserved
These bits are always read as 0. The write value
should always be 0.
9 to 2 TRA

R/W 8-bit Immediate Data
1, 0


R
Reserved
These bits are always read as 0. The write value
should always be 0.
Rev. 3.00 Jan. 18, 2008 Page 218 of 1458
REJ09B0033-0300