SH7720 Datasheet, PDF (663/1524 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 18 Serial Communication Interface with FIFO (SCIF)
Bit Bit Name Initial Value R/W Description
8
TSF
0
R/(W)* Transmit Data Stop Flag
Indicates that the number of transmit data matches the
value set in SCTDSR.
0: Transmit data number does not match the value set
in SCTDSR
[Clearing conditions]
• Power-on reset, manual reset
• Writing 0 after reading TSF = 1
1: Transmit data number matches the value set in
SCTDSR
7
ER
0
R/(W)* Receive Error
Indicates that a framing error or parity error occurred
during reception in asynchronous mode.*¹
0: Receive is normally completed without any framing or
parity error
[Clearing conditions]
Power-on reset, manual reset
ER is read as 1, then written to with 0.
1: A framing error or a parity error has occurred during
receiving
[Setting conditions]
• The stop bit is 0 after checking whether or not the
last stop bit of the received data is 1 at the end of
one-data receive.*²
• The total number of 1's in the received data and in
the parity bit does not match the even/odd parity
specification specified by the O/E bit in the SCSMR.
Notes: 1. Indicates clearing the RE bit to 0 in SCSCR
does not affect the ER bit, which retains its
previous value. Even if a receive error
occurs, the received data is transferred to
SCFRDR and the receive operation is
continued. Whether or not the data read
from SCRDR includes a receive error can
be detected by the FER and PER bits in
SCSSR.
2. n the stop mode, only the first stop bit is
checked; the second stop bit is not checked.
Rev. 3.00 Jan. 18, 2008 Page 601 of 1458
REJ09B0033-0300