SH7720 Datasheet, PDF (125/1524 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 2 CPU
2.6 Instruction Set
2.6.1 Instruction Set Based on Functions
Table 2.5 shows the instructions classified by function.
Table 2.5 CPU Instruction Types
Type
Kinds of
Instruction
Data transfer 5
instructions
Arithmetic 21
operation
instructions
Op Code
MOV
MOVA
MOVT
SWAP
XTRCT
ADD
ADDC
ADDV
CMP/cond
DIV1
DIV0S
DIV0U
DMULS
DMULU
DT
EXTS
EXTU
MAC
MUL
Function
Number of
Instructions
Data transfer
39
Effective address transfer
T bit transfer
Upper/lower swap
Extraction of middle of linked registers
Binary addition
33
Binary addition with carry
Binary addition with overflow check
Comparison
Division
Signed division initialization
Unsigned division initialization
Signed double-precision multiplication
Unsigned double-precision multiplication
Decrement and test
Sign extension
Zero extension
Multiply-and-accumulate, double-
precision multiply-and-accumulate
Double-precision multiplication
(32 × 32 bits)
Rev. 3.00 Jan. 18, 2008 Page 63 of 1458
REJ09B0033-0300