SH7720 Datasheet, PDF (749/1524 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 21 Serial I/O with FIFO (SIOF)
Bit
9
8
7 to 2
Initial
Bit Name Value R/W Description
TXE
0
R/W Transmit Enable
0: Disables data transmission from the SIOFTxD pin
1: Enables data transmission from the SIOFTxD pin
• This bit setting becomes valid at the start of the next
frame (at the rising edge of the SIOFSYNC signal).
• When the 1 setting for this bit becomes valid, the
SIOF issues a transmit transfer request according to
the setting of the TFWM bit in SIFCTR. When
transmit data is stored in the transmit FIFO,
transmission of data from the SIOFTxD pin begins.
• This bit is initialized upon a transmit reset.
This bit is initialized in module stop mode.
RXE
0
R/W Receive Enable
0: Disables data reception from SIOFRxD
1: Enables data reception from SIOFRxD
• This bit setting becomes valid at the start of the next
frame (at the rising edge of the SIOFSYNC signal).
• When the 1 setting for this bit becomes valid, the
SIOF begins the reception of data from the
SIOFRxD pin. When receive data is stored in the
receive FIFO, the SIOF issues a reception transfer
request according to the setting of the RFWM bit in
SIFCTR.
• This bit is initialized upon receive reset.
This bit is initialized in module stop mode.

All 0
R
Reserved
These bits are always read as 0. The write value should
always be 0.
Rev. 3.00 Jan. 18, 2008 Page 687 of 1458
REJ09B0033-0300