SH7720 Datasheet, PDF (1082/1524 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 30 SIM Card Module (SIM)
30.5 Usage Notes
The following matters should be noted when using the smart card interface.
(1) Receive Data Timing and Receive Margin
When SCSMPL holds its initial value, the smart card interface operates at a basic clock frequency
372 times the transfer rate.
During reception, the smart card interface samples the falling edge of the start bit using the serial
clock for internal synchronization. Receive data is captured internally at the rising edge of the
186th serial clock pulse. This is shown in figure 30.7.
372 clock pulses
Basic clock
186 clock pulses
0
185
371 0
185
371 0
Received data
(RXD)
Start bit
D0
D1
Synchronization
sampling timing
Data sampling
timing
Figure 30.7 Receive Data Sampling Timing in Smart Card Mode
Rev. 3.00 Jan. 18, 2008 Page 1020 of 1458
REJ09B0033-0300