SH7720 Datasheet, PDF (777/1524 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 21 Serial I/O with FIFO (SIOF)
21.4.4 Register Allocation of Transfer Data
(1) Transmit/Receive Data
Writing and reading of transmit/receive data are performed for the following registers.
• Transmit data writing: SITDR (32-bit access)
• Receive data reading: SIRDR (32-bit access)
Figure 21.5 shows the transmit/receive data and the SITDR and SIRDR bit alignment.
(a) 16-bit stereo data
31
24 23
16 15
87
0
L-channel data
R-channel data
(b) 16-bit monaural data
31
24 23
16 15
87
0
Data
(c) 8-bit monaural data
31
24 23
16 15
87
0
Data
(d) 16-bit stereo data (left and right same audio output) data
31
24 23
16 15
87
0
Data
Figure 21.5 Transmit/Receive Data Bit Alignment
Note: In the figure, only the shaded areas are transmitted or received as valid data. Data in
unshaded areas is not transmitted or received.
Monaural or stereo can be specified for transmit data by the TDLE bit and TDRE bit in SITDAR.
Monaural or stereo can be specified for receive data by the RDLE bit and RDRE bit in SIRDAR.
To achieve left and right same audio output while stereo is specified for transmit data, specify the
TLREP bit in SITDAR. Tables 21.6 and 21.7 show the audio mode specification for transmit data
and that for receive data, respectively.
Rev. 3.00 Jan. 18, 2008 Page 715 of 1458
REJ09B0033-0300