SH7720 Datasheet, PDF (247/1524 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 4 Memory Management Unit (MMU)
Figure 4.11 shows the case where the IX bit in MMUCR is 0.
When an MMU exception occurs, the virtual page number of the virtual address that caused the
exception is set in PTEH by hardware. The way is set in the RC bit in MMUCR for each exception
according to the rules (see section 4.2.4, MMU Control Register (MMUCR)). Consequently, if the
LDTLB instruction is issued after setting only PTEL in the MMU exception processing routine,
TLB entry recording is possible. Any TLB entry can be updated by software rewriting of PTEH
and the RC bits in MMUCR.
As the LDTLB instruction changes address translation information, there is a risk of destroying
address translation information if this instruction is issued in the P0, U0, or P3 area. Make sure,
therefore, that this instruction is issued in the P1 or P2 area. Also, an instruction associated with an
access to the P0, U0, or P3 area (such as the RTE instruction) should be issued at least two
instructions after the LDTLB instruction.
MMUCR
31
0
Index
9
0
SV 0 0 RC 0 TF IX AT
Way selection
PTEH register
31
17
VPN
12 10 8
0
VPN 0 ASID
PTEL register
31 29 28 10
0
0 0 0 PPN 0 V 0 PR SZ C D SH 0
Write
Way 0 to 3
Write
0 VPN(31 to 17) VPN(11 to 10) ASID(7 to 0) V PPN(28 to 10) PR(1 to 0) SZ C D SH
31
Address array
Data array
Figure 4.11 Operation of LDTLB Instruction
Rev. 3.00 Jan. 18, 2008 Page 185 of 1458
REJ09B0033-0300