SH7720 Datasheet, PDF (882/1524 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 25 USB Function Controller (USBF)
25.3.14 Interrupt Enable Register 3 (IER3)
IER3 enables the interrupt requests of the interrupt flag register 3. When an interrupt flag is set to
1 while the corresponding bit of each interrupt is set to 1, the interrupt request set in the interrupt
select register 3 is issued.
Bit Bit Name
7 to 4 
3
EP5 TR IE
2
EP5 TS IE
1
EP4 TF IE
0
EP4 TS IE
Initial Value R/W Description
All 0
R Reserved
These bits are always read as 0. The write value should
always be 0.
0
R/W EP5 TR Interrupt Enable
0
R/W EP5 TS Interrupt Enable
0
R/W EP4 TF Interrupt Enable
0
R/W EP4 TS Interrupt Enable
25.3.15 Interrupt Enable Register 4 (IER4)
IER4 enables the interrupt requests of the interrupt flag register 4. When an interrupt flag is set to
1 while the corresponding bit of each interrupt is set to 1, the interrupt request set in the interrupt
select register 4 is issued.
Bit Bit Name
7 to 1 
0
TMOUT IE
Initial Value R/W Description
All 0
R Reserved
These bits are always read as 0. The write value
should always be 0.
0
R/W TMOUT Interrupt Enable
Rev. 3.00 Jan. 18, 2008 Page 820 of 1458
REJ09B0033-0300