SH7720 Datasheet, PDF (797/1524 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 22 Analog Front End Interface (AFEIF)
Section 22 Analog Front End Interface (AFEIF)
This LSI has an AFE interface that supports softwaremodem. This AFE interface can efficiently
execute the modem processing, because it includes 128 stages of FIFO for each of transmission
and reception. This AFE interface also includes the interface to data access arrangement (DAA)
such as dial pulse generator circuit and ringing detection. Therefore, it is possible to establish a
modem system with a minimum of hardware.
22.1 Features
• Serial interface with FIFO
• Clock synchronized serial interface
• Transmit/receive FIFO size is 16 bits (maximum) × 128 words
• Transmit/receive interrupt threshold size is programmable
• Dial pulse generator circuit is included
• Ringing detection (calling signal) function is included
Figure 22.1 shows a block diagram of AFEIF.
32
16
Bus I/F
Peripheral bus
16
Ringing
detector
16
Dial pulse
generator
16
Control
registers ¹⁶
16
Transmit FIFO
16 bits × 128 words ¹⁶
16
Receive FIFO
16 bits × 128 words
AFE control word
AFE status word
HC control
P/S
S/P
AFE_RDET AFE_RLYCNT AFE_FS AFE_SCLK AFE_TXOUT AFE_HC1 AFE_RXIN
Figure 22.1 Block Diagram of AFE Interface
Rev. 3.00 Jan. 18, 2008 Page 735 of 1458
REJ09B0033-0300