SH7720 Datasheet, PDF (803/1524 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 22 Analog Front End Interface (AFEIF)
Each interrupt mask flag is able to prohibit interrupt generation of each interrupt that indicated in
interrupt status flag. Every mask bits are automatically set when TE or RE bit are modified to 1.
TFEM and THEM are 1 when TE = 0. RFFM and RHFM are 1 when RE = 0. Each mask bit is
reset as 1.
Bit
Bit Name
15 to 12 
11
TFEM
10
RFFM
9
THEM
8
RHFM
7 to 4 
3
TFE
Initial Value
All 0
1
1
1
1
All 0
1
R/W Description
R Reserved
These bits are always read as 0. The write
value should always be 0.
R/W Transmit FIFO Empty Interrupt Mask
0: TFE Interrupt enable
1: TFE interrupt masked
R/W Receive FIFO Full Interrupt Mask
0: RFF Interrupt enable
1: RFF Interrupt masked
R/W Threshold of Transmit FIFO Empty Interrupt
Mask
0: THE Interrupt enable
1: THE Interrupt masked
R/W Threshold of Receive FIFO Full Interrupt Mask
0: RHF Interrupt enable
1: RHF Interrupt masked
R Reserved
These bits are always read as 0. The write
value should always be 0.
R Transmit FIFO Empty Interrupt
0: Normal state
[Clearing condition]
• Data are written into FIFO
1: TxFIFO empty interrupt
[Setting conditions]
• Reset
• No effective data in area of FIFO
• TE bit (ACTR1) is set to 0 (TFEM bit is set
to 1)
Rev. 3.00 Jan. 18, 2008 Page 741 of 1458
REJ09B0033-0300