SH7720 Datasheet, PDF (1490/1524 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Item
Page Revision (See Manual for Details)
31.3.7 Response Registers 0 to 1040 Changed
16 and D (RSPR0 to RSPR16 and
RSPRD)
Bit
Bit Name ^{Initial Value}
R/W
7 to 5 
All 0

4 to 0
RSPRD
All 0
R/W
31.3.14 Interrupt Status Registers 1051 Amended
0 and 1 (INTSTR0 and INTSTR1)
Bit Bit Name Description
2 CRCERI CRC Error Flag
[Setting condition]
When a CRC error for command response
or receive data, and CRC status error for
transmission data response are detected
while CRCERIE = 1.
For any non-R2 command response, CRC
is checked when the RTY4 in RSPTYR is
set for enabling.
For the R2 command response, CRC is
not checked; therefore, this flag is not set.
[Clearing condition]
Write 0 after reading CRCERI = 1.
Note: When the CRC error occurs,
halt the command sequence by
setting the CMDOFF bit to 1.
31.3.15 Transfer Clock Control
Register (CLKON)
1053 Changed
The 33-MHz peripheral clock is needed, and bits
CSEL3 to CSEL0 should be set to 0001 for a 16.5-
Mbps transfer clock of the MMCIF.
1053 Changed
Bit Bit Name Description
7 CLKON Clock On
0: Stops the transfer clock output from the
CLK/SCLK pin.
1: Outputs the transfer clock from the
CLK/SCLK pin.
Rev. 3.00 Jan. 18, 2008 Page 1428 of 1458
REJ09B0033-0300