SH7720 Datasheet, PDF (310/1524 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 8 Interrupt Controller (INTC)
Table 8.2 Interrupt Sources and IPRA to IPRJ
Register
Bits 15 to 12
Bits 11 to 8
Bits 7 to 4
Bits 3 to 0
IPRA
TMU0
TMU1
TMU2
RTC
IPRB
WDT
REF
SIM
Reserved*
IPRC
IRQ3
IRQ2
IRQ1
IRQ0
IPRD
Reserved*
TMU (TMU_SUNI) IRQ5
IRQ4
IPRE
DMAC (1)
Reserved*
LCDC
SSL
IPRF
ADC
DMAC (2)
USBF
CMT
IPRG
IPRH
SCIF0
PINTA
SCIF1
PINTB
Reserved*
TPU
Reserved*
I²C
IPRI
SIOF0
SIOF1
MMC
PCC
IPRJ
Reserved*
USBH
SDHI
AFEIF
Note: * Reserved. Always read as 0. The write value should always be 0. The SSL and SDHI-
related bits are effective only for the models that include them. Reserved bits apply if
they are not included.
As shown in table 8.2, on-chip peripheral module or IRQ interrupts are assigned to four 4-bit
groups in each register. These 4-bit groups (bits 15 to 12, bits 11 to 8, bits 7 to 4, and bits 3 to 0)
are set with values from H'0 (0000) to H'F (1111). Setting H'0 means priority level 0 (masking is
requested); H'F means priority level 15 (the highest level).
Rev. 3.00 Jan. 18, 2008 Page 248 of 1458
REJ09B0033-0300