SH7720 Datasheet, PDF (251/1524 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 4 Memory Management Unit (MMU)
• Software (TLB Miss Handler) Operations
The software searches the page tables in external memory and allocates the required page table
entry. Upon retrieving the required page table entry, software must execute the following
operations:
A. Write the value of the physical page number (PPN) field and the protection key (PR), page
size (SZ), cacheable (C), dirty (D), share status (SH), and valid (V) bits of the page table
entry recorded in the address translation table in the external memory into the PTEL
register.
B. If using software for way selection for entry replacement, write the desired value to the RC
field in MMUCR.
C. Issue the LDTLB instruction to load the contents of PTEH and PTEL into the TLB.
D. Issue the return from exception handler (RTE) instruction to terminate the handler routine
and return to the instruction stream. Issue the RTE instruction after issuing two instructions
from the LDTLB instruction.
4.5.2 TLB Protection Violation Exception
A TLB protection violation exception results when the virtual address and the address array of the
selected TLB entry are compared and a valid entry is found to match, but the type of access is not
permitted by the access rights specified in the PR field. TLB protection violation exception
processing includes both hardware and software operations.
• Hardware Operations
In a TLB protection violation exception, this hardware executes a set of prescribed operations,
as follows:
A. The VPN field of the virtual address causing the exception is written to the PTEH register.
B. The virtual address causing the exception is written to the TEA register.
C. Either exception code H'0A0 for a load access, or H'0C0 for a store access, is written to the
EXPEVT register.
D. The PC value indicating the address of the instruction in which the exception occurred is
written into SPC (if the exception occurred in a delay slot, the PC value indicating the
address of the related delayed branch instruction is written into SPC).
E. The contents of SR at the time of the exception are written to SSR.
F. The MD bit in SR is set to 1 to place the privileged mode.
G. The BL bit in SR is set to 1 to mask any further exception requests.
H. The RB bit in SR is set to 1.
I. The way that generated the exception is set in the RC field in MMUCR.
Rev. 3.00 Jan. 18, 2008 Page 189 of 1458
REJ09B0033-0300