SH7720 Datasheet, PDF (678/1524 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 18 Serial Communication Interface with FIFO (SCIF)
to 0 in transmitting. Set the TFRST bit in the SCFCR to 1 and reset the SCFTDR before TE is set
again to start transmission.
When an external clock is used, the clock should not be stopped during initialization or subsequent
operation. SCIF operation becomes unreliable if the clock is stopped.
Figure 18.2 is a sample flowchart for initializing the SCIF.
Initialization
Clear TE and RE bits in SCSCR to 0 (1)
Set TFRST and RFRST bits in
SCFCR to 1
Set CKE1 and CKE0
bits in SCSCR2 (leaving TE and RE
bits cleared to 0)
Set operating clock source in SCSMR (2)
Set value in SCBRR
(3)
Wait
(1) Set the clock selection in SCSCR.
Be sure to clear bits RIE TIE, TE, and RE
to 0.
(2) Set the operating clock source in SCSMR.
(3) Write a value corresponding to the bit rate
into SCBRR.
(Not necessary if an external clock is used.)
(4) Wait at least one bit interval, then set the
TE bit or RE bit in SCSR to 1. Also set the
RIE and TIE bits.
Setting the TE and RE bits enables the
TxD and RxD pins to be used. When
transmitting, the SCIF will go to the mark
state; when receiving, it will go to the idle
state.
No
1-bit interval elapsed?
(4)
Yes
Set RTRG1, RTRG0,
TTRG1, and TTRG0 in SCFCR
Clear TFRST and RFRST bits to 0
Set TE and RE bits in
SCSCR to 1,and set RIE,
and TIE bits
End
Figure 18.2 Sample SCIF Initialization Flowchart
Rev. 3.00 Jan. 18, 2008 Page 616 of 1458
REJ09B0033-0300