SH7720 Datasheet, PDF (541/1524 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 13 Power-Down Modes
(1) Power-On Reset
1. Driving the RESETP pin low.
2. While the WT/IT bit in WTCSR is set to 1 and the RSTS bit is cleared to 0, the WDT starts
counting and continues until it overflows.
3. Generation of the H-UDI reset (for details on the H-UDI reset, refer to section 36, User
Debugging Interface (H-UDI)).
(2) Manual Reset
1. Driving the RESETM pin low.
2. While the WT/IT bit in WTCSR and the RSTS bit are set to 1, the WDT starts counting and
continues until it overflows.
13.2 Input/Output Pins
Table 13.2 lists the pin configuration related to power-down modes.
Table 13.2 Pin Configuration
Pin Name
Abbreviation I/O
Description
Status 1 output
STATUS1
Output Operating state of the processor.
Status 0 output
STATUS0
HH: Reset
HL: Sleep mode
LH: Standby mode
Power-on reset
input
Manual-reset input
RESETP
RESETM
Input
LL: Normal operation
Power-on reset occurs at low-level.
Input Manual reset occurs at low-level.
Chip active
CA
Input Hardware standby mode entered at low-level.
Rev. 3.00 Jan. 18, 2008 Page 479 of 1458
REJ09B0033-0300