SH7720 Datasheet, PDF (718/1524 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 20 I²C Bus Interface (IIC)
Initial
Bit
Bit Name Value R/W Description
4
NACKF 0
R/W No Acknowledge Detection Flag
[Setting condition]
• When no acknowledge is detected from the receive
device in transmission while the ACKE bit in ICIER is
1
[Clearing condition]
• When 0 is written in NACKF after reading NACKF = 1
3
STOP
0
R/W Stop Condition Detection Flag
[Setting conditions]
• In master mode: when a stop condition is detected
after frame transfer is completed
• In slave mode: when a stop condition is detected after
the address set in SAR matches the salve address
that comes as the first byte after the detection of a
start condition
[Clearing condition]
• When 0 is written in STOP after reading STOP = 1
2
AL/OVE 0
R/W Arbitration Lost Flag/Overrun Error Flag
This flag indicates that arbitration was lost in master
mode with the I²C bus format.
When two or more master devices attempt to seize the
bus at nearly the same time, if the I²C bus interface
detects data differing from the data it sent, it sets AL to 1
to indicate that the bus has been taken by another
master.
[Setting conditions]
• If the internal SDA and SDA pin disagree at the rise of
SCL in master transmit mode
• When the SDA pin outputs high in master mode while
a start condition is detected
[Clearing condition]
• When 0 is written in AL/OVE after reading AL/OVE =
1
Rev. 3.00 Jan. 18, 2008 Page 656 of 1458
REJ09B0033-0300