SH7720 Datasheet, PDF (786/1524 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 21 Serial I/O with FIFO (SIOF)
(4) Reception in Slave Mode
Figure 21.12 shows an example of settings and operation for slave mode reception.
No.
Flow Chart
Start
1
Set SIMDR, SISCR, SITDAR,
SIRDAR, SICDAR, and SIFCTR
2
Set the RXE bit in SICTR to 1
Store SIOFRXD receive data in SIRDR
3
synchronously with SIOFSYNC
SIOF Settings
SIOF Operation
Set operating mode, serial clock,
slot positions for transmit/receive
data, slot position for control data,
and FIFO request threshold value
Set to enable reception
Enable reception when the
frame synchronous signal is
input
Issue receive transfer request
according to the receive
FIFO threshold value
4
RDREQ = 1? ^No
Yes
Reception
5
Read SIRDR
Read receive data
Transfer
No
ended?
6
Yes
Clear the RXE bit in SICTR to 0
End
Set to disable reception
End reception
Figure 21.12 Example of Receive Operation in Slave Mode
Rev. 3.00 Jan. 18, 2008 Page 724 of 1458
REJ09B0033-0300