SH7720 Datasheet, PDF (374/1524 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 9 Bus State Controller (BSC)
Initial
Bit
Bit Name Value R/W Description
17
BW1
0
R/W Number of Burst Wait Cycles
16
BW0
0
R/W Specify the number of wait cycles to be inserted between
the second or later access cycles in burst access.
00: 0 cycles
01: 1 cycle
10: 2 cycles
11: 3 cycles
15 to 11 
All 0 R Reserved
These bits are always read as 0. The write value should
always be 0.
10
W3
1
R/W Number of Access Wait Cycles
9
W2
0
R/W Specify the number of wait cycles to be inserted in the first
8
W1
1
R/W ^{access cycle.}
7
W0
0
R/W ^{0000: 0 cycles}
0001: 1 cycle
0010: 2 cycles
0011: 3 cycles
0100: 4 cycles
0101: 5 cycles
0110: 6 cycles
0111: 8 cycles
1000: 10 cycles
1001: 12 cycles
1010: 14 cycles
1011: 18 cycles
1100: 24 cycles
1101: Reserved (setting prohibited)
1110: Reserved (setting prohibited)
1111: Reserved (setting prohibited)
Rev. 3.00 Jan. 18, 2008 Page 312 of 1458
REJ09B0033-0300