SH7720 Datasheet, PDF (750/1524 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 21 Serial I/O with FIFO (SIOF)
Initial
Bit
Bit Name Value R/W Description
1
TXRST 0
R/W Transmit Reset
0: Does not reset transmit operation
1: Resets transmit operation
• This bit setting becomes valid immediately. This bit
should be cleared to 0 before setting the register to
be initialized.
• When the 1 setting for this bit becomes valid, the
SIOF immediately sets transmit data from the
SIOFTxD pin to 1, and initializes the transmit data
register and transmit-related status. The following
are initialized.
 SITDR
 SITCR
 Transmit FIFO write pointer and read pointer
 TCRDY, TFEMP, and TDREQ bits in SISTR
 TXE bit
0
RXRST 0
R/W Receive Reset
0: Does not reset receive operation
1: Resets receive operation
• This bit setting becomes valid immediately. This bit
should be cleared to 0 before setting the register to
be initialized.
• When the 1 setting for this bit becomes valid, the
SIOF immediately disables reception from the
SIOFRxD pin, and initializes the receive data
register and receive-related status. The following
are initialized.
 SIRDR
 SIRCR
 Receive FIFO write pointer and read pointer
 RCRDY, RFFUL, and RDREQ bits in SISTR
 RXE bit
Rev. 3.00 Jan. 18, 2008 Page 688 of 1458
REJ09B0033-0300