SH7720 Datasheet, PDF (1084/1524 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 30 SIM Card Module (SIM)
5. If a normal frame is received, the pin retains its high-impedance state at the timing for
transmission of error signals.
nth transmit frame
Retransmit frame
(n+1)th transmit frame
RDRF
PER
Ds D0 D1 D2 D3 D4 D5 D6 D7 DP DE
(DE)
Ds D0 D1 D2 D3 D4 D5 D6 D7 DP
Ds D0 D1 D2 D3 D4
(5)
(2)
(4)
(1)
(3)
Figure 30.8 Retransmission when Smart Card Interface is in Receive Mode
(b) Retransmission when the smart card interface is in transmit mode (T = 0)
Figure 30.9 shows retransmit operations when the smart card interface is in transmit mode. Step
(1) to step (4) of figure 30.9 correspond to the following operation
1. After completion of transmission of one frame, if an error signal is returned from the receive
side, the ERS bit in SCSSR is set to 1. If the RIE bit in SCSCR is set to enable, an ERI request
is issued. The ERS bit in SCSSR should be cleared to 0 before the sampling timing for the next
parity bit.
2. In T = 0 mode, the TEND bit in SCSSR is not set for a frame when an error signal indicating
an error is received.
3. If no error signal is returned from the receive side, the ERS bit in SCSSR is not set.
4. If no error signal is returned from the receive side, it is assumed that transmission of one
frame, including retransmission, is completed, and the TEND bit in SCSSR is set to 1. At this
time, if the TIE bit in SCSCR is set to enable, a TEI interrupt request is issued.
Rev. 3.00 Jan. 18, 2008 Page 1022 of 1458
REJ09B0033-0300