SH7720 Datasheet, PDF (274/1524 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 5 Cache
5.4.3 Usage Examples
(1) Invalidating Specific Entries
Specific cache entries can be invalidated by writing 0 to the entry’s V bit in the memory-mapped
cache access. When the A bit is 1, the tag address specified by the write data is compared to the
tag address within the cache selected by the entry address, and a match is found, the entry is
written back if the entry’s U bit is 1 and the V bit and U bit specified by the write data are written.
If no match is found, there is no operation. In the example shown below, R0 specifies the write
data and R1 specifies the address.
; R0=H'01100010; VPN=B'0000 0001 0001 0000 0000 00, U=0, V=0
; R1=H'F0000088; address array access, entry=B'00001000, A=1
;
MOV.L R0,@R1
(2) Reading the Data of a Specific Entry
To read the data field of a specific entry is enabled by the memory-mapped cache access. The
longword indicated in the data field of the data array in figure 5.4 is read into the register. In the
example shown below, R0 specifies the address and R1 shows what is read.
; R0=H'F100 004C; data array access, entry=B'00000100
; Way = 0, longword address = 3
;
MOV.L @R0,R1 ; Longword 3 is read.
Rev. 3.00 Jan. 18, 2008 Page 212 of 1458
REJ09B0033-0300