SH7720 Datasheet, PDF (588/1524 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 15 16-Bit Timer Pulse Unit (TPU)
Initial
Bit Bit Name Value R/W Description
1
TGFB
0
R/(W)* Compare Flag B
Status flag that indicates the occurrence of TGRB compare
match.
[Clearing conditions]
When 0 is written to TGFB after reading TGFB = 1
[Setting conditions]
When TCNT = TGRB
0
TGFA
0
R/(W)* Output Compare Flag A
Status flag that indicates the occurrence of TGRA compare
match.
[Clearing conditions]
When 0 is written to TGFA after reading TGFA = 1
[Setting conditions]
When TCNT = TGRA
Note: * Only 0 can be written, to clear the flag.
15.3.6 Timer Counters (TCNT)
The TCNT registers are 16-bit readable/writable counters. The TPU has four TCNT counters, one
for each channel.
The TCNT counters are initialized to H'0000 by a reset.
The TCNT counters are not initialized in standby mode, sleep mode, or module standby.
15.3.7 Timer General Registers (TGR)
The TGR registers are 16-bit registers. The TPU has 16 TGR registers, four each for channels 0
and 3. TGRC and TGRD can also be designated for operation as buffer registers*. The TGR
registers are initialized to H'FFFF by a reset. These registers are not initialized in standby mode,
sleep mode, or module standby.
Note: * TGR buffer register combinations are TGRA—TGRC and TGRB—TGRD.
Rev. 3.00 Jan. 18, 2008 Page 526 of 1458
REJ09B0033-0300