SH7720 Datasheet, PDF (783/1524 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 21 Serial I/O with FIFO (SIOF)
21.4.7 Transmit and Receive Procedures
(1) Transmission in Master Mode
Figure 21.9 shows an example of settings and operation for master mode transmission.
No.
Flow Chart
Start
1
Set SIMDR, SISCR, SITDAR,
SIRDAR, SICDAR, and SIFCTR
2
Set the SCKE bit in SICTR to 1
3
Start SIOFSCK output
4
Set the FSE and TXE bits
in SICTR to 1
SIOF Settings
SIOF Operation
Set operating mode, serial clock,
slot positions for transmit/receive
data, slot position for control data,
and FIFO request threshold value
Set operation start for baud rate
generator
Output serial clock
Set the start for frame synchronous Output frame synchronous
signal output and enable
signal and issue transmit
transmission
transfer request*
5
TDREQ = 1? ^No
Yes
6
Set SITDR
Set transmit data
7
Transmit SITDR from SIOFTXD
synchronously with SIOFSYNC
Transmit
Transfer No
ended?
8
Yes
Clear the TXE bit in SICTR to 0
Set to disable transmission
End transmission
9
Set the FSE bit in SICTR to 0
Set the MSSEL bit in SISCR to 1
Set BRDV=111
and BPRS=00000 in SISCR
10
Add pulse (0→1→0)
to the TXRST in SISCR
Reset the master clock source
and baud rate in SISCR
11
Change other No
transmit mode?
Yes
End
12
Start the setting FSE=0,
TXE=0 and other bit.
Synchronize this LSI internal
frame with FSE=0 if restarting
transmit later.
Execute internal initialization
of the bit rate generator
if restarting transmit later.
'No' requires further setting
if transmission is not restarted
(No).
When returning to the same
transmit mode from here,
go back to No.4, FSE setting,
on this flowchart.
Go to "Start" on each flowchart.
Note: * When interrupts due to transmit data underflow are enabled, after setting the no. 6 transmit data, the
TXE bit should be set to 1.
Figure 21.9 Example of Transmit Operation in Master Mode
Rev. 3.00 Jan. 18, 2008 Page 721 of 1458
REJ09B0033-0300