SH7720 Datasheet, PDF (482/1524 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 10 Direct Memory Access Controller (DMAC)
10.3.6 DMA Extended Resource Selectors 0 to 2 (DMARS0 to DMARS2)
DMARS are 16-bit readable/writable registers that specify the DMA transfer sources from
peripheral modules in each channel. DMARS0 specifies for channels 0 and 1, DMARS1 specifies
for channels 2 and 3, and DMARS2 specifies for channels 4 and 5. This register can set the
transfer request of SCIF0, SIOF1, MMC, CMT (channels 0 to 4), SIM, USBF, SIOF0, SIOF1, and
SDHI.
When MID/RID other than the values listed in table 10.2 is set, the operation of this LSI is not
guaranteed. The transfer request from DMARS is valid only when the resource select bits (RS3 to
RS0) have been set to B'1000 for CHCR_0 to CHCR_5 registers. Otherwise, even if DMARS has
been set, transfer request source is not accepted.
• DMARS0
Initial
Bit
Bit Name Value R/W Description
15
C1MID5 0
14
C1MID4 0
13
C1MID3 0
R/W Transfer request module ID5 to ID0 for DMA channel 1
R/W ^(MID)
R/W ^{See table 10.2.}
12
C1MID2 0
R/W
11
C1MID1 0
R/W
10
C1MID0 0
R/W
9
C1RID1 0
8
C1RID0 0
R/W Transfer request register ID1 and ID0 for DMA channel 1
R/W ^(RID)
See table 10.2.
7
C0MID5 0
6
C0MID4 0
5
C0MID3 0
R/W Transfer request module ID5 to ID0 for DMA channel 0
R/W ^(MID)
R/W ^{See table 10.2.}
4
C0MID2 0
R/W
3
C0MID1 0
R/W
2
C0MID0 0
R/W
1
C0RID1 0
0
C0RID0 0
R/W Transfer request register ID1 and ID0 for DMA channel 0
R/W ^(RID)
See table 10.2.
Rev. 3.00 Jan. 18, 2008 Page 420 of 1458
REJ09B0033-0300