SH7720 Datasheet, PDF (564/1524 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 14 Timer Unit (TMU)
14.2.1 Timer Start Register (TSTR)
TSTR is an 8-bit readable/writable register that selects whether to operate or halt the timer
counters (TCNT).
TSTR is initialized to H'00 at a power-on reset, manual reset, or in module stop mode. It is
retained in sleep mode and standby mode.
Initial
Bit
Bit Name Value R/W Description
7 to 3 —
All 0
R
Reserved
These bits are always read as 0. The write value should
always be 0.
2
STR2
0
R/W Counter Start 2
Selects whether to operate or halt timer counter 2
(TCNT_2).
0: TCNT_2 count halted
1: TCNT_2 counts
1
STR1
0
R/W Counter Start 1
Selects whether to operate or halt timer counter 1
(TCNT_1).
0: TCNT_1 count halted
1: TCNT_1 counts
0
STR0
0
R/W Counter Start 0
Selects whether to operate or halt timer counter 0
(TCNT_0).
0: TCNT_0 count halted
1: TCNT_0 counts
Rev. 3.00 Jan. 18, 2008 Page 502 of 1458
REJ09B0033-0300