SH7720 Datasheet, PDF (520/1524 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 11 Clock Pulse Generator (CPG)
11.3 Clock Operating Modes
Table 11.2 shows the relationship between the mode control pins (MD2 to MD0) combinations
and the clock modes. Table 11.3 shows the available combinations of the values of the clock
modes and frequency control register (FRQCR).
Table 11.2 Clock Operating Modes
Pin Values
Mode MD2 MD1 MD0
0
0
0
0
1
0
0
1
2
0
1
0
7
1
1
1
Clock I/O
Source Output
EXTAL CKIO
EXTAL CKIO
Crystal CKIO
resonator
CKIO 
PLL2
On/Off
ON
(x 1)
ON
(x 4)
ON
(x 4)
OFF
PLL1
On/Off
ON
(x 1, 2, 3, 4)
ON
(x 1, 2, 3, 4)
ON
(x 1, 2, 3, 4)
ON
(x 1, 2, 3, 4)
CKIO
Frequency
(EXTAL)
(EXTAL) x 4
(Crystal) x 4
(CKIO)
Mode 0: The LSI is supplied with a clock that is wave-formed by PLL circuit 2 after receiving an
external clock from the EXTAL pin. The frequency of CKIO ranges from 24.00 to 66.67
MHz, because the input clock frequency ranges from 24.00 to 66.67 MHz.
Mode 1: The clock supplied to the internal circuitry in the LSI is generated by PLL circuit 2
quadrupling the frequency after receiving an external clock from the EXTAL pin.
Therefore, the frequency of a clock generated outside the LSI can be lower. The
frequency of CKIO ranges from 40.00 to 66.67 MHz, because an input clock with a
frequency range of 10.00 to 16.67 MHz is used.
Mode 2: The clock is generated by an on-chip crystal oscillator, and its frequency is quadrupled by
PLL circuit 2. Therefore, the frequency of a clock generated outside the LSI can be lower.
The frequency of CKIO ranges from 40.00 to 66.67 MHz, because a crystal oscillator with
a frequency range of 10.00 to 16.67 MHz is used.
Mode 7: The CKIO pin works as an input pin in this mode. The frequency of the external clock
supplied to the LSI is multiplied by the setting ratio after the external clock is input via the
CKIO pin and wave-formed by PLL circuit 1. This mode is suitable for connecting a
synchronous DRAM, because the change in the load in the CKIO pin is controlled by PLL
circuit 1.
Rev. 3.00 Jan. 18, 2008 Page 458 of 1458
REJ09B0033-0300