SH7720 Datasheet, PDF (354/1524 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 9 Bus State Controller (BSC)
Initial
Bit Bit Name Value R/W Description
10 DPRTY1 0
R/W DMA Burst Transfer Priority
9
DPRTY0 0
R/W Specify the priority for a refresh request/bus mastership request
during DMA burst transfer.
00: Accepts a refresh request and bus mastership request
during DMA burst transfer
01: Accepts a refresh request but does not accept a bus
mastership request during DMA burst transfer
10: Accepts neither a refresh request nor a bus mastership
request during DMA burst transfer
11: Reserved (Setting prohibited)
8
DMAIW2 0
7
DMAIW1 0
6
DMAIW0 0
R/W Wait States between Access Cycles when DMA Single Address
R/W ^{is Transferred}
R/W ^{Specify the number of idle cycles to be inserted after an access}
to an external device with DACK when DMA single address
transfer is performed. The method of inserting idle cycles
depends on the contents of DMAIWA.
000: No idle cycle inserted
001: 1 idle cycle inserted
010: 2 idle cycles inserted
011: 4 idle cycled inserted
100: 6 idle cycled inserted
101: 8 idle cycle inserted
110: 10 idle cycles inserted
111: 12 idle cycled inserted
5
DMAIWA 0
R/W Method of Inserting Wait States between Access Cycles when
DMA Single Address is Transferred
Specifies the method of inserting the idle cycles specified by the
DMAIW1 and DMAIW0 bits. Clearing this bit will make this LSI
insert the idle cycles when another device, which includes this
LSI, drives the data bus after an external device with DACK
drove it. Setting this bit will make this LSI insert the idle cycles
even when the continuous accesses to an external device with
DACK are performed.
0: Inserts the idle cycles when another device drives the data
bus after an external device with DACK drove it.
1: Inserts the idle cycles every time when an external device
with DACK is accessed.
Rev. 3.00 Jan. 18, 2008 Page 292 of 1458
REJ09B0033-0300